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april 2009 doc id 14489 rev 2 1/64 64 stmpe811 advanced resistive touch screen controller with 8-bit gpio expander features 8 gpios 1.8 - 3.3 v operating voltage integrated 4-wire touch screen controller interrupt output pin wakeup feature on each i/o spi and i 2 c interface up to 2 devices sharing the same bus in i 2 c mode (1 address line) 8-input 12-bit adc 128-depth buffer touch screen controller touch screen movement detection algorithm 25 kv air-gap esd protection (system level) 4 kv hbm esd protection (device level) applications portable media players game consoles mobile and smartphones gps description the stmpe811 is a gpio (general purpose input/output) port expander able to interface a main digital asic via the two-line bidirectional bus (i 2 c). a separate gpio expander is often used in mobile multimedia platforms to solve the problems of the limited amount of gpios typically available on the digital engine. the stmpe811 offers great flexibility, as each i/o can be configured as input, output or specific functions. the device has been designed with very low quiescent current and includes a wakeup feature for each i/o, to optimize the power consumption of the device. a 4-wire touch screen cont roller is built into the stmpe811. the touch screen controller is enhanced with a movement tracking algorithm (to avoid excessive data), a 128 x 32 bit buffer and programmable active window feature. qfn16 (3x3) table 1. device summary order code package packaging STMPE811QTR qfn16 tape and reel www.st.com
contents stmpe811 2/64 doc id 14489 rev 2 contents 1 stmpe811 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration and f unctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 i2c and spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 i2c features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 spi protocol definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 register reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2 register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.3 termination of data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 spi timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.1 spi timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 stmpe811 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 system and identificati on registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 analog-to-digital converte r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 touch screen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.1 driver and switch control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11 touch screen controller pr ogramming sequence . . . . . . . . . . . . . . . . 45
stmpe811 contents doc id 14489 rev 2 3/64 12 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13 gpio controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.0.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.0.2 power-up reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 16 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
list of tables stmpe811 4/64 doc id 14489 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. pin configuration for in2, in3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. pin configuration for x+, y+, x-, y-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. interface selection pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. i2c address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9. spi timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. spi timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. register summary map table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12. system and identification registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 13. adc controller register summary table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 table 14. adc conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. touch screen controller register summary table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. touch screen controller data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 table 17. touch screen parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 18. gpio control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 19. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 20. power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 21. dc electrical characteristics (-40 c to 85 c) all gpios comply to jedec standard jesd- 8-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 22. ac electrical characteristics (-40 c to 85 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 23. adc specification (-40 c to 85 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 24. switch drivers specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 25. voltage reference specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 26. package mechanical data for qfn16 (3 x 3 x 1 mm) - 0.50 pitch . . . . . . . . . . . . . . . . . . . 59 table 27. exposed pad variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 28. footprint dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 29. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
stmpe811 list of figures doc id 14489 rev 2 5/64 list of figures figure 1. stmpe811 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. stmpe811 pin configuration (top through view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. stmpe811 interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. stmpe811 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. i 2 c timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. read and write modes (random and sequential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. spi timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. interrupt system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. touch screen controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 figure 10. window tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 11. sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12. package outline for qfn16 (3 x 3 x 1 mm) - 0.50 pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 13. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 14. carrier tape for qfn16 (3 x 3 x 1 mm) - 0.50 pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 15. reel information for qfn16 (3 x 3 x 1 mm) - 0.50 pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
stmpe811 functional overview stmpe811 6/64 doc id 14489 rev 2 1 stmpe811 functional overview the stmp811 consists of the following blocks: i 2 c and spi interface analog-to-digital converver (adc) touch screen controller (tsc) driver and switch control unit temperature sensor gpio controller figure 1. stmpe811 functional block diagram s witche s a nd driver s gnd s clk/clk s dat/ c s a 0 /d a t a o u t vcc int adc , t s c vref therm a l s en s e rc o s cill a tor d a t a in t s c: to u ch s creen controlle r gpio controller i c / s pi interf a ce 2 gpio 0-7 /adc in 0-7 /mode /ref-, ref+
stmpe811 pin configuration and functions doc id 14489 rev 2 7/64 2 pin configuration and functions figure 2. stmpe811 pin configuration (top through view) table 2. pin assignments pin name function 1 y- y-/gpio-7 2 int interrupt output (v cc domain), open drain 3 a0/data out i 2 c address in reset, data out in spi mode (v cc domain) 4sclki 2 c/spi clock (v cc domain) 5sdati 2 c data/spi cs (v cc domain) 6v cc 1.8 ? 3.3 v supply voltage 7 data in spi data in (v cc domain) 8 in0 in0/gpio-0 9in1 in1/gpio-1/mode in reset state, mode selects the type of serial interface "0" - i 2 c "1" - spi 10 gnd ground 11 in2 in2/gpio-2 12 in3 in3/gpio-3 13 x+ x+/gpio-4 14 vio supply for touch screen driver and gpio 15 y+ y+/gpio-5 16 x- x-/gpio-6 16 15 14 13 5 6 7 8 1 2 3 4 12 11 10 9 stmpe811
pin configuration and functions stmpe811 8/64 doc id 14489 rev 2 2.1 pin functions the stmpe811 is designed to provide maximum features and flexibility in a very small pin- count package. most of the pins are multi-functional. ta bl e 3 and ta bl e 4 show how to select the pin?s function. table 3. pin configuration for in2, in3 pin / control register gpio_af = 1 gpio_af = 0 adc control 1 bit 1 = don?t care adc control 1 bit 1 = 0 adc control 1 bit 1 = 1 in0 gpio-0 adc in1 gpio-1 adc in2 gpio-2 adc external reference + in3 gpio-3 adc external reference - table 4. pin configuration for x+, y+, x-, y- pin / control register gpio_af = 1 gpio_af = 0 tsc control 1 bit 0 = don?t care tsc control 1 bit 0 = 0 tsc control 1 bit 0 = 1 x+ gpio-4 adc tsc x+ y+ gpio-5 adc tsc y+ x- gpio-6 adc tsc x- y- gpio-7 adc tsc y-
stmpe811 i2c and spi interface doc id 14489 rev 2 9/64 3 i 2 c and spi interface 3.1 interface selection the stmpe811 interfaces with the host cpu via a i 2 c or spi interface. the pin in_1 allows the selection of interface protocol at reset state. figure 3. stmpe811 interface table 5. interface selection pins pin i 2 c function spi function reset state 3 address 0 data out cpha for spi 4clockclock ? 5 sdata cs cpol_n for spi 7 ? data in ? 9modei 2 c set to ?0? set to ?1? for spi spi i/f module i c i/f module din dout clk cs sdat sclk a0 mux unit 2
i2c interface stmpe811 10/64 doc id 14489 rev 2 4 i 2 c interface the addressing scheme of stmpe811 is designed to allow up to 2 devices to be connected to the same i 2 c bus. figure 4. stmpe811 i 2 c interface for the bus master to communicate to the slave device, the bus master must initiate a start condition and be followed by the slave device address. accompanying the slave device address, is a read/write bit (r/w). the bit is set to 1 for read and 0 for write operation. if a match occurs on the slave device address, the corresponding device gives an acknowledge on the sda during the 9 th bit time. if there is no match, it deselects itself from the bus by not responding to the transaction. figure 5. i 2 c timing diagram table 6. i 2 c address addr0 address 00x82 10x88 addr0 sc lk sdat sc lk sdat gnd vcc stmpe811 ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
stmpe811 i2c interface doc id 14489 rev 2 11/64 4.1 i 2 c features the features that are supported by the i 2 c interface are listed below: i 2 c slave device operates at 1.8 v compliant to philips i 2 c specification version 2.1 supports standard (up to 100 kbps) and fast (up to 400 kbps) modes start condition a start condition is iden tified by a falling edge of sdata while sclk is stable at high state. a start condition must precede any data/command transfer. the device continuously monitors for a start condition and does not respond to any transaction unless one is encountered. stop condition a stop condition is identified by a rising edge of sdata while sclk is stable at high state. a stop condition terminates communication between the slave device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the slave device into idle mode. when the slave device is in idle mode, it is ready to receive the next i 2 c transaction. a stop condition at the end of a write command stops the write operation to registers. acknowledge bit the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter releases the sdata after sending eight bits of data. during the ninth bit, the receiver pulls the sdata low to acknowledge the receipt of the eight bits of data. the receiver may leave the sdata in high state if it does not acknowledge the receipt of the data. table 7. i 2 c timing symbol parameter min typ max uni f scl scl clock frequency 0 ? 400 khz t low clock low period 1.3 ?? s t high clock high period 600 ?? ns t f sda and scl fall time ? 300 ns t hd:sta start condition hold time (after this period the first clock is generated) 600 ?? ns t su:sta start condition setup time (only relevant for a repeated start period) 600 ?? ns t su:dat data setup time 100 ?? ns t hd:dat data hold time 0 ?? s t su:sto stop condition setup time 600 ?? ns t buf time the bus must be free before a new transmission can start 1.3 ?? s
i2c interface stmpe811 12/64 doc id 14489 rev 2 4.2 data input the device samples the data input on sdata on the rising edge of the sclk. the sdata signal must be stable during the rising edge of sclk and the sdata signal must change only when sclk is driven low. figure 6. read and write modes (random and sequential) table 8. operating modes mode byte programming sequence read 1 start, device address, r/w = 0, register address to be read restart, device address, r/w = 1, data read, stop if no stop is issued, the data read can be continuously performed. if the register address falls within t he range that allows an address auto- increment, then the register addres s auto-increments internally after every byte of data being read. write 1 start, device address, r/w = 0, register address to be written, data write, stop if no stop is issued, the data writ e can be continuously performed. if the register address falls within the range that allows address auto- increment, then the register addres s auto-increments internally after every byte of data being written in. for those register addresses that fall within a non-incremental address range, the address will be kept static throughout the entire write op eration. refer to the memory map table for the address ranges that are auto and non-increment. start r/w=0 ack device address reg address ack device address ack r/w=1 data read no ack stop one byte read start r/w=0 ack device address reg address ack restart device address ack r/w=1 data read ack more than one byte read ack no ack stop data read + 1 data read + 2 start r/w=0 ack device address reg address ack data to be written ack stop one byte write more than one byte read start r/w=0 ack device address reg address ack data to write ack stop data to write + 2 ack ack data to write + 1 master slave am00775v1
stmpe811 i2c interface doc id 14489 rev 2 13/64 4.3 read operation a write is first performed to load the register address into the address counter but without sending a stop condition. then, the bus master sends a restart condition and repeats the device address with the r/w bit set to 1. the slave device acknowledges and outputs the content of the addressed byte. if no additional data is to be read, the bus master must not acknowledge the byte and terminates the transfer with a stop condition. if the bus master acknowledges the data byte, then it can continue to perform the data reading. to terminate the stream of data bytes, the bus master must not acknowledge the last output byte, and be followed by a stop condition. if the address of the register written into the address counter falls within the range of addresses that has the auto-increment function, the data being read will be coming from consecutive ad dresses, which the internal address counter automatically increments after each byte output. after the last memory address, the address counter 'rolls-over' and the device continues to output data from the memory address of 0x00. similarly, for the regi ster address that falls within a non-increment range of addresses, the output data byte comes from the same address (which is the address referred by the address counter). acknowledgement in read operation for the above read command, the slave device waits, after each byte read, for an acknowledgement during the ninth bit time. if the bus master does not drive the sda to a low state, then the slave device terminates and switches back to its idle mode, waiting for the next command. 4.4 write operations a write is first performed to load the register address into the address counter without sending a stop condition. after the bus master receives an acknowledgement from the slave device, it may start to send a data byte to the register (referred by the address counter). the slave device again acknowledges and the bus master terminates the transfer with a stop condition. if the bus master needs to write more data, it can continue the write operation without issuing the stop condition. whether the address counter autoincrements or not after each data byte write depends on the address of the register written into the address counter. after the bus master writes the last data byte and the slave device acknowledges the receipt of the last data, the bus master may terminate the write operation by sending a stop condition. when the address counter reaches the last memory address, it 'rolls-over' to the next data byte write.
spi interface stmpe811 14/64 doc id 14489 rev 2 5 spi interface the spi (serial peripheral interface) in st mpe811 uses a 4-wire communication connection (data in, data out, clk, cs). in the diagram, ?data in? is referred to as mosi (master out slave in) and ?data out? is referred to as miso (master in slave out). 5.1 spi protocol definition the spi follows a byte-sized transfer protocol. a ll transfers begin with an assertion of cs_n signal (falling edge). t he protocol for reading and writin g is different and the selection between a read and a write cycle is dependent on the first captured bit on the slave device. a '1' denotes a read operation and a '0' denotes a write operation. the spi protocol defined in this section is shown in figure 3 . the following are the main features supported by this spi implementation. support of 1 mhz maximum clock frequency. support for autoincrement of address for both read and write. full duplex support for read operation. daisy chain configuration support for write operation. robust implementation that can filter glitches of up to 50 ns on the cs_n and scl pins. support for all 4 modes of spi as define d by the cpha, cpol bits on spicon. 5.1.1 register reading the following steps need to be followed for the register read through the spi. 1. assert cs_n by driving a '0' on this pin. 2. drive a '1' on the first scl launch clock on mosi to select a read operation. 3. the next 7 bits on mosi denote the 7-bit register address (msb first). 4. the next address byte can now be transmitted on the mosi. if the autoincrement bit is set, the following address transmitted on the mosi is ignored. internally, the address is incremented. if the autoincrement bit is not set, then the following byte denotes the address of the register to be read next. 5. read data is transmitted by the slave device on the miso (msb first), starting from the launch clock following the last address bit on the mosi. 6. full duplex read operation is achieved by transmitting the next address on mosi while the data from the previous address is available on miso. 7. to end the read operation, a dummy address of all 0's is sent on mosi.
stmpe811 spi interface doc id 14489 rev 2 15/64 5.1.2 register write the following steps need to be followed for register write through spi. 1. assert cs_n by driving a '0' on this pin. 2. drive a '0' on the first scl launch clock on mosi to select a write operation. 3. the next 7 bits on mosi denote the 7-bit register address (msb first). 4. the next byte on the mosi denotes data to be written. 5. the following transmissions on mosi are considered byte-sized data. the register address to which the following data is written depends on whether the autoincrement bit in the spicon register is set. if this bit has been set previously, the register address is incremented for data writes. 5.1.3 termination of data transfer a transfer can be terminated before the last launch edge by deasserting the cs_n signal. if the last launch clock is detected, it is a ssumed that the data transfer is successful.
spi interface stmpe811 16/64 doc id 14489 rev 2 5.2 spi timing modes the spi timing modes are defined by cpha and cpol,cpha and cpol are read from the "sdat" and "a0" pins during power-up reset. the following four modes are defined according to this setting. the clocking diagrams of these modes are show n in on reset. the device always operates in mode 0. once the bits are set in the spicon register, the mode change takes effect on the next transaction defined by the cs_n pin being deasserted and asserted. 5.2.1 spi timing definition table 9. spi timing modes cpol_n (sdat pin) cpol cpha (addr pin) mode 1000 1011 0102 0113 table 10. spi timing specification symbol description timing unit min typ max t css cs_n falling to first capture clock 1 ?? s t cl clock low period 500 ?? ns t ch clock high period 500 ?? ns t ldi launch clock to mosi data valid ?? 20 ns t ldo launch clock to miso data valid ?? 330 s t di data on mosi valid 1 ?? s t ccs last clock edge to cs_n high 1 ?? s t csh cs_n high period 2 ?? s
stmpe811 spi interface doc id 14489 rev 2 17/64 figure 7. spi timing specification t cscl cs_n high to first clock edge 300 ?? ns t csz cs_n high to tri-state on miso 1 ?? s table 10. spi timing specification (continued) symbol description timing unit min typ max
stmpe811 registers stmpe811 18/64 doc id 14489 rev 2 6 stmpe811 registers this section lists and describes the registers of the stmpe811 device, starting with a register map and then provides detailed descriptions of register types. table 11. register summary map table address register name bit type reset value function 0x00 chip_id 16 r 0x0811 device identification 0x02 id_ver 8 r 0x03 revision number 0x01 for engineering sample 0x03 for final silicon 0x03 sys_ctrl1 8 r/w 0x00 reset control 0x04 sys_ctrl2 8 r/w 0x0f clock control 0x08 spi_cfg 8 r/w 0x01 spi in terface configuration 0x09 int_ctrl 8 r/w 0x00 interrupt control register 0x0a int_en 8 r/w 0x00 interrupt enable register 0x0b int_sta 8 r 0x10 interrupt status register 0x0c gpio_en 8 r/w 0x00 gpio interrupt enable register 0x0d gpio_int_sta 8 r 0x00 gpio interrupt status register 0x0e adc_int_en 8 r/w 0x00 adc interrupt enable register 0x0f adc_int_sta 8 r 0x00 adc interrupt status register 0x10 gpio_set_pin 8 r/w 0x00 gpio set pin register 0x11 gpio_clr_pin 8 r/w 0x00 gpio clear pin register 0x12 gpio_mp_sta 8 r/w 0x00 gpio monitor pin state register 0x13 gpio_dir 8 r/w 0x00 gpio direction register 0x14 gpio_ed 8 r/w 0x00 gpio edge detect register 0x15 gpio_re 8 r/w 0x00 gpio rising edge register 0x16 gpio_fe 8 r/w 0x00 gpio falling edge register 0x17 gpio_af 8 r/w 0x00 alternate function register 0x20 adc_ctrl1 8 r/w 0x9c adc control 0x21 adc_ctrl2 8 r/w 0x01 adc control 0x22 adc_capt 8 r/w 0xff to initiate adc data acquisition 0x30 adc_data_ch0 16 r 0x0000 adc channel 0 0x32 adc_data_ch1 16 r 0x0000 adc channel 1
stmpe811 stmpe811 registers doc id 14489 rev 2 19/64 0x34 adc_data_ch2 16 r 0x0000 adc channel 2 0x36 adc_data_ch3 16 r 0x0000 adc channel 3 0x38 adc_data_ch4 16 r 0x0000 adc channel 4 0x3a adc_data_ch5 16 r 0x0000 adc channel 5 0x3c adc_data_ch6 16 r 0x0000 adc channel 6 0x3e adc_data_ch7 16 r 0x0000 adc channel 7 0x40 tsc_ctrl 8 r/w 0x90 4-wire touch screen controller setup 0x41 tsc_cfg 8 r/w 0x00 touch screen controller configuration 0x42 wdw_tr_x 16 r/w 0x0fff window setup for top right x 0x44 wdw_tr_y 16 r/w 0x0fff window setup for top right y 0x46 wdw_bl_x 16 r/w 0x0000 window setup for bottom left x 0x48 wdw_bl_y 16 r/w 0x0000 window setup for bottom left y 0x4a fifo_th 8 r/w 0x00 fifo level to generate interrupt 0x4b fifo_sta 8 r/w 0x20 current status of fifo 0x4c fifo_size 8 r 0x00 current filled level of fifo 0x4d tsc_data_x 16 r 0x0000 data port for touch screen controller data access 0x4f tsc_data_y 16 r 0x0000 data port for touch screen controller data access 0x51 tsc_data_z 8 r 0x0000 data port for touch screen controller data access 0x52 tsc_data_xyz 32 r 0x00000000 data port for touch screen controller data access 0x56 tsc_fract_x yz 8 0x00 touch screen controller fraction_xyz 0x57 tsc_data 8 r 0x00 data port for touch screen controller data access 0x58 tsc_i_drive 8 r/w 0x00 touch screen controller drive i 0x59 tsc_shield 8 r/w 0x00 touch screen controller shield 0x60 temp_ctrl 8 r/w 0x00 temperature sensor setup table 11. register summary map table (continued) address register name bit type reset value function
stmpe811 registers stmpe811 20/64 doc id 14489 rev 2 0x61 temp_data 8 r 0x00 temperature data access port 0x62 temp_th 8 r/w 0x00 threshold for temperature controlled interrupt table 11. register summary map table (continued) address register name bit type reset value function
stmpe811 system and identification registers doc id 14489 rev 2 21/64 7 system and identification registers chip_id device identification address: 0x00 type: r reset: 0x0811 description: 16-bit device identification id_ver revision number address: 0x02 type: r reset: 0x03 (0x01 for engineering samples) description: 16-bit revision number table 12. system and identification registers map address register name bit type reset function 0x00 chip_id 16 r 0x0811 device identification 0x02 id_ver 8 r 0x03 revision number (0x03 for engineering sample) 0x03 sys_ctrl1 8 r/w 0x00 reset control 0x04 sys_ctrl2 8 r/w 0x0f clock control 0x08 spi_cfg 8 r/w 0x01 spi interface configuration
system and identification registers stmpe811 22/64 doc id 14489 rev 2 sys_ctrl1 reset control address: 0x03 type: r/w reset: 0x00 description: the reset control register enables to reset the device sys_ctrl2 clock control address: 0x04 type: r/w reset: 0x0f description: this register enables to switch off the clock supply 76543 2 1 0 reserved soft_reset hibernate [7:2] reserved [1] soft_reset : reset the stmpe811 using the serial communication interface [0] hibernate : force the device into hibernation mode. forcing the device into hibernation mode by writing ?1? to this bit would disable the hot-key feature. if the hot-key feature is requir ed, use the default auto-hibernation mode. 76543 2 1 0 ???? ts_off gpio_off tsc_off adc_off [7:4] reserved [3] ts_off : switch off the clock supply to the temperature sensor 1: switches off the clock s upply to the temperature sensor [2] gpio_off : switch off the clock supply to the gpio 1: switches off the clock supply to the gpio [1] tsc_off : switch off the clock supplyt o the touch screen controller 1: switches off the clock suppl y to the touch screen controller [0] adc_off : switch off the clock supply to the adc 1: switches off the clock supply to the adc
stmpe811 system and identification registers doc id 14489 rev 2 23/64 spi_cfg spi interface configuration address: 0x08 type: r/w reset: 0x01 description: spi interface configuration register 76543 2 1 0 reserved auto_incr spi_clk_mod1 spi_clk_mod0 [7:3] reserved [2] auto_incr : this bit defines whether the spi transaction fo llows an addressing scheme that internally autoincrements or not [1] spi_clk_mod1 : this bit reflects the value of the scad/a0 pin during power-up reset [0] spi_clk_mod0 : this bit reflects the value of the scad/a0 pin during power-up reset
interrupt system stmpe811 24/64 doc id 14489 rev 2 8 interrupt system the stmpe811 uses a 2-tier interrupt structure. the adc interrupts and gpio interrupts are ganged as a single bit in the ?interrupt status register?. the interrupts from the touch screen controller and temperature sensor can be seen directly in the interrupt status register. figure 8. interrupt system diagram gpio interrupt status fifo status, tsc touch, temp sensor and interrupt enable interrupt status and gpio interrupt enable and adc interrupt enable adc interrupt status
stmpe811 interrupt system doc id 14489 rev 2 25/64 int_ctrl interrupt control register address: 0x09 type: r/w reset: 0x00 description: the interrupt control register is used to enable the interruption from a system-related interrupt source to the host. 76543 2 1 0 reserved int_polarity int_type global_int [7:3] reserved [2] int_polarity : this bit sets the int pin polarity 1: active high/rising edge 0: active low/falling edge [1] int_type : this bit sets the type of interrupt signal required by the host 1: edge interrupt 0: level interrupt [0] global_int : this is master enabl e for the interrupt system 1: global interrupt 0: stops all interrupts
interrupt system stmpe811 26/64 doc id 14489 rev 2 int_en interrupt enable register address: 0x0a type: r/w reset: 0x00 description: the interrupt enable register is used to enable the interruption from a system related interrupt source to the host. int_sta interrupt status register address: 0x0b type: r reset: 0x10 description: the interrupt status register monitors the status of the interruption from a particular interrupt source to the host. regardless of whether the int_en bits are enabled, the int_sta bits are still updated. writing '1' to this regist er clears the corresponding bits. writing '0' has no effect. 76543 2 1 0 gpio adc temp_sens fifo_empty fifo_full fifo_0flow fifo_th touch_det [7] gpio : any enabled gpio interrupts [6] adc : any enabled adc interrupts [5] temp_sens : temperature threshold triggering [4] fifo_empty : fifo is empty [3] fifo_full : fifo is full [2] fifo_oflow : fifo is overflowed [1] fifo_th : fifo is equal or above threshold value. [0] touch_det : touch is detected 76543 2 1 0 gpio adc temp_sens fifo_empty fifo_full fifo_oflow fifo_th touch_det [7] gpio : any enabled gpio interrupts [6] adc : any enabled adc interrupts [5] temp_sens : temperature threshold triggering [4] fifo_empty : fifo is empty [3] fifo_full : fifo is full [2] fifo_oflow : fifo is overflowed [1] fifo_th : fifo is equal or above threshold value. this bit is set when fifo level equals to threshold value. it will only be asserted again if fifo level drops to < threshold value, and increased back to threshold value. [0] touch_det : touch is detected
stmpe811 interrupt system doc id 14489 rev 2 27/64 gpio_int_en gpio interrupt enable register address: 0x0c type: r/w reset: 0x10 description: the interrupt status register monitors the status of the interruption from a particular interrupt source to the host. regardless of whether the ier bits are enabled, the isr bits are still updated. writing '1' to this re gister clears the corresponding bits. writing '0' has no effect. gpio_int_sta gpio interrupt status register address: 0x0d type: r/w reset: 0x00 description: the gpio interrupt status register monitors the status of the interruption from a particular gpio pin interrupt source to the host. regardless of whether or not the gpio_sta bits are enabled, the gpio_sta bi ts are still updated. the isg[7:0] bits are the interrupt status bits corresponding to the gpio[7:0] pins. writing '1' to this register clears the corresponding bits. writing '0' has no effect. 76543 2 1 0 ieg[x] [7:0] ieg[x]: interrupt enable gpio mask (where x = 7 to 0) 1: writing ?1? to the ie[x] bit enables the interruption to the host 76543 2 1 0 isg[x] [7:0] isg[x] : gpio interrupt status (where x = 7 to 0) read: interrupt status of the gpio[x]. reading the register will clear any bits that have been set to '1' write: writing to this register has no effect
analog-to-digital converter stmpe811 28/64 doc id 14489 rev 2 9 analog-to-digital converter an 8-input,12-bit analog-to-digital converter (adc) is integrated in the stmpe811. the adc can be used as a generic analog-to-digital converter, or as a touch screen controller capable of controlling a 4-wire resistive touch screen. table 13. adc controller register summary table address register name size description 0x20 adc_ctrl1 8 adc control 0x21 adc_ctrl2 8 adc control 0x22 adc_capt 8 adc channel data capture 0x30 adc_data_ch0 8 adc channel 0 (in3/gpio-3) 0x32 adc_data_ch1 8 adc channel 1 (in2/gpio-2) 0x34 adc_data_ch2 8 adc channel 2 (in1/gpio-1) 0x36 adc_data_ch3 8 adc channel 3 (in0-gpio-0) 0x38 adc_data_ch4 8 adc channel 4 (tsc) 0x3a adc_data_ch5 8 adc channel 5 (tsc) 0x3c adc_data_ch6 8 adc channel 6 (tsc) 0x3e adc_data_ch7 8 adc channel 7 (tsc)
stmpe811 analog-to-digital converter doc id 14489 rev 2 29/64 adc_ctrl1 adc control 1 address: 0x20 type: r/w reset: 0x9c description: adc control register. 765432 1 0 reserved sample_time2 sample_time1 sample_time0 mod_12b reserved ref_sel reserved [7] reserved [6:4] sample_timen : adc conversion time in number of clock 000: 36 001: 44 010: 56 011: 64 100: 80 101: 96 110: 124 111: not valid [3] mod_12b : selects 10 or 12-bit adc operation 1: 12 bit adc 0: 10 bit adc [2] reserved [1] ref_sel : selects between internal or external reference for the adc 1: external reference 0: internal reference [0] reserved
analog-to-digital converter stmpe811 30/64 doc id 14489 rev 2 adc_ctrl2 adc control 2 address: 0x21 type: r/w reset: 0x01 description: adc control. adc_capt adc channel data capture address: 0x22 type: r/w reset: 0xff description: to initiate adc data acquisition . 76543 2 1 0 reserved adc_freq_1 adc_freq_0 [7] reserved [6] reserved [5] reserved [4] reserved [3] reserved [2] reserved [1:0] adc_freq : selects the clock speed of adc 00: 1.625 mhz typ. 01: 3.25 mhz typ. 10: 6.5 mhz typ. 11: 6.5 mhz typ. 76543 2 1 0 ch[7:0] [7:0] ch[7:0] : adc channel data capture write '1' to initiate data acquisition for the corresponding channel. writing '0' has no effect. reads '1' if conversion is completed. reads '0' if conversion is in progress.
stmpe811 analog-to-digital converter doc id 14489 rev 2 31/64 adc_data_chn adc channel data registers address: add address type: r/w reset: 0x0000 description: adc data register 0-7 (data_chn=0 -7) the adc in stmpe811 operates on an internal rc clock with a typical frequency of 6.5 mhz. the total conversion time in adc mode depends on the "sampletime" setting, and the clock division field 'freq'. the following table shows the conversion time based on 6.5 mhz, 3.25 mhz and 1.625 mhz clock. 11109876543 2 1 0 data[11:0] [11:0] data[11:0] : adc channel data if tsc is enabled, ch3-0 is used for tsc and all readings to these channels give 0x0000 table 14. adc conversion time sample time setting conversion time in adc clock 6.5 mhz (154 ns) 3.25 mhz (308 ns) 1.625 mhz (615 ns) 000 36 5.5 s (180 khz) 11 s (90 khz) 22 s (45 khz) 001 44 6.8 s (147 khz) 13.6 s (74 khz) 27 s (36 khz) 010 56 8.6 s (116 khz) 17.2 s (58 khz) 34.4 s (29 khz) 011 64 9.9 s (101 khz) 19.8 s (51 khz) 39.6 s (25 khz) 100 80 12.3 s(81.5 khz) 24.6 s (41 khz) 49.2 s (20 khz) 101 96 14.8 s (67.6 khz) 28.8 s (33 khz) 59.2 s (17 khz) 110 124 19.1 s (52.3 khz) 38.2 s (26 khz) 56.4 s (13 khz)
touch screen controller stmpe811 32/64 doc id 14489 rev 2 10 touch screen controller the stmpe811 is integrated with a hard-wired touch screen controller for 4-wire resistive type touch screen. the touch screen controller is able to operate completely autonomously, and will interrupt the connec ted cpu only when a pre-defined event occurs. figure 9. touch screen controller block diagram 10.1 driver and switch control unit the driver and switch control unit allows coordination of the adc and the mux/switch. with the coordination of this unit, a stream of data is produced at a selected frequency. the touch screen drivers can be configured with 2 current ratings: 20 ma or 50 ma. in the case where multiple touch-down on the screen is causing a short, the current from the driver is limited to these values. tolerance of these current setting is +/- 25%. movement tracking the "tracking index" in the tsc_ctrl register specifies a value, which determines the distance between the current touch position and the previous touch position. if the distance is shorter than the tracking index, it is discarded. the tracking is calculated by summation of the horizontal and vertical movement. movement is only reported if: (current x - previously reported x) + (current y - previously reported y) > tracking index if pressure reporting is enabled (x/y/z), an increase in pres sure will override the movement tracking and report the new data set, even if x/y is within the previous tracking index. this is to ensure that a slow touch will not be discarded. if pressure data is not used, select x/y mode in touch screen data acquisition. (opmode field in tsccontrol register). s movement & window tracking 10/12 bit adc switch & drivers driver & switch control fifo & interrupt control fifo
stmpe811 touch screen controller doc id 14489 rev 2 33/64 window tracking the -wdw_x and wdw_y registers allow to pre-set a sub-window in the touch screen such that any touch position that is ou tside the sub-window will be discarded. figure 10. window tracking fifo fifo has a depth of 128 sectors. this is enough for 128 sets of touch data at maximum resolution (2 x 12 bits). fifo can be programmed to generate an interrup t when it is filled to a pre-determined level. sampling the stmpe811 touch screen controller has an internal 180 khz, 12-bit adc able to execute autonomous driving/sampling. each "sample" consists of 4 adc readings that provide the x and y locations, as well as the touch pressure. figure 11. sampling active window top right coordin a te s bottom left coordin a te s adc takes x reading settling period drive x adc takes y reading settling period drive y
touch screen controller stmpe811 34/64 doc id 14489 rev 2 oversampling and averaging function the stmpe811 touch screen controller can be configured to oversample by 2/4/8 times and provide the averaged value as final output. this feature helps to reduce the effect of surrounding noise. table 15. touch screen controller register summary table address register name bit type function 0x40 tsc_ctrl 8 r/w 4-wire touch screen controller setup 0x41 tsc_cfg 8 r/w tsc configuration register 0x42 wdw_tr_x 16 r/w window setup for top right x 0x44 wdw_tr_y 16 r/w window setup for top right y 0x46 wdw_tr_x 16 r/w window setup for bottom left x 0x48 wdw_tr_y 16 r/w window setup for bottom left y 0x4a fifo_th 8 r/w fifo level to generate interrupt 0x4b fifo_sta 8 r/w current status of fifo 0x4c fifo_size 8 r current filled level of fifo 0x4d tsc_data_x 16 r data port for tsc data access 0x4f tsc_data_y 16 r data port for tsc data access 0x51 tsc_data_z 8 r data port for tsc data access 0x52 tsc_data_xyz 32 r data port for tsc data access 0x56 tsc_fract_z 8 r/w touch screen controller fraction_z 0x57 tsc_data 8 r touch screen controller data access port 0x58 tsc_i_drive 8 r/w touch screen controller drive i 0x59 tsc_shield 8 r/w touch screen controller shield
stmpe811 touch screen controller doc id 14489 rev 2 35/64 tsc_ctrl touch screen controller control register address: 0x40 type: r/w reset: 0x90 description: 4-wire touch screen controller (tsc) setup. 76543 2 1 0 tsc_sta track op_mod en [7] tsc_sta : tsc status reads '1' when touch is detected reads '0' when touch is not detected writing to this register has no effect [6:4] track : tracking index 000: no window tracking 001: 4 010: 8 011: 16 100: 32 101: 64 110: 92 111: 127 [3:1] op_mod : tsc operating mode 000: x, y, z acquisition 001: x, y only 010: x only 011: y only 100: z only this field cannot be written on, when en = 1 [0] en : enable tsc
touch screen controller stmpe811 36/64 doc id 14489 rev 2 tsc_cfg touch screen controller configuration register address: 0x41 type: r/w description: touch screen controller configuration register. 76543 2 1 0 ave_ctrl_1 ave_ctrl_0 touch_det _delay_2 touch_det _delay_1 touch_det _delay_0 settling_2 settling_1 settling_0 [7:6] [ ave_ctrl_1/0 : average control 00=1 sample 01=2 samples 10=4 samples 11=8 samples [5:3] touch_det_delay_2/1/0 : touch detect delay 000 - 10 s 001 - 50 s 010 = 100 s 011 = 500 s 100=1ms 101=5ms 110 = 10 ms 111 = 50 ms [2:0] settling : panel driver settling time (1) 000 = 10 s 001 = 100 s 010 = 500 s 011=1ms 100=5ms 101 = 10 ms 110 = 50 ms 111=100ms 1. for large panels (> 6?), a capacitor of 10 nf is reco mmended at the touch screen terminals for noise filtering. in this case, settling time of 1 ms or more is recommended.
stmpe811 touch screen controller doc id 14489 rev 2 37/64 wdw_tr_x window setup for top right x address: 0x42 type: r/w reset: 0x0fff description: window setup for top right x coordinates . wdw_tr_y window setup for top right y address: 0x44 type: r/w reset: 0x0fff description: window setup for top right y coordinates . 7 6543 2 1 0 tr_x [11:0] [11:0] tr_x: bit 11:0 of top right x coordinates 7 6543 2 1 0 tr_y [11:0] [11:0] tr_x : bit 11:0 of top right y coordinates
touch screen controller stmpe811 38/64 doc id 14489 rev 2 wdw_bl_x window setup for bottom left x address: 0x46 type: r/w reset: 0x0000 description: window setup for bottom left x coordinates . wdw_bl_y window setup for bottom left y address: 0x48 type: r/w reset: 0x0000 description: window setup for bottom left y coordinates . fifo_th fifo threshold address: 0x4a type: r/w reset: 0x00 description: triggers an interrupt upon reaching or exceeding the threshold value. this field must not be set as zero. 7 6543 2 1 0 bl_x [11:0] [11:0] bl_x: bit 11:0 of bottom left x coordinates 7 6543 2 1 0 bl_y [11:0] [11:0] bl_x : bit 11:0 of bottom left y coordinates 76543 2 1 0 fifo_th [7:0] fifo_th : touch screen controller fifo threshold
stmpe811 touch screen controller doc id 14489 rev 2 39/64 fifo_sta fifo status address: 0x4b type: r/w reset: 0x20 description: current status of fifo.. fifo_size fifo size address: 0x4c type: r reset: 0x00 description: current number of samples available. 765432 1 0 fifo_oflow fifo_full fifo_empty f ifo_th_trig reserved fifo_reset [7] fifo_oflow : reads 1 if fifo is overflow [6] fifo_full : reads 1 if fifo is full [5] fifo_empty: reads 1 if fifo is empty [4] fifo_th_trig : 0 = current fifo size is st ill below the threshold value 1 = current fifo size is at or beyond the threshold value [3:1] reserved [0] fifo_reset : write '0' : fifo put out of reset mode write '1' : resets fifo. all data in fifo will be cleared. when tsc is enabled, fifo resets automatically. 76543 2 1 0 reserved fifo_size [7:0] fifo_size : number of samples available
touch screen controller stmpe811 40/64 doc id 14489 rev 2 tsc_data_x tsc_data_x address: 0x4d type: r reset: 0x0000 description: bit 11:0 of y data. 11109876543 2 1 0 datay[11:0] [11:0] datay[11:0 ]: bit 11:0 of y data
stmpe811 touch screen controller doc id 14489 rev 2 41/64 tsc_data_y tsc_data_y address: 0x4f type: r reset: 0x0000 description: bit 11:0 of y data. tsc_data_z tsc_data_z address: 0x51 type: r reset: 0x0000 description: bit 7:0 of z data. 11109876543 2 1 0 datay[11:0] [11:0] datay[11:0] : bit 11:0 of y data 76543 2 1 0 dataz[7:0] [7:0] dataz[7:0] : bit 7:0 of z data
touch screen controller stmpe811 42/64 doc id 14489 rev 2 tsc_data_xyz touch screen controller data address: 0x57 (auto-increment), 0xd7 (non-auto-increment) type: r reset: 0x00 description: data port for tsc data access the data format from the tsc_data register depends on the setting of "opmode" field in tsc_ctrl register. the samples acquired are accessed in "packed samples". the size of each "packed sample" depends on which mode the touch screen controller is operating in. the tsc_data register can be accessed in 2 modes: autoincrement non autoincrement to access the 128-sets buffer, the non autoincrement mode should be used. 76543 2 1 0 data [11:0] data : data bytes from tsc fifo table 16. touch screen controller data register tsc_ctrl in operation mode number of bytes to read from tsc_data_xyz byte0 byte1 byte2 byte3 000 4 [11:4] of x [3:0] of x [11:8] of y [7:0] of y [7:0] of z 001 3 [11:4] of x [3:0] of x [11:8] of y [7:0] of y ? 010 2 [11:4] of x [3:0] of x ?? 011 2 [11:4] of y [3:0] of y ?? 100 1 [7:0] of z - ??
stmpe811 touch screen controller doc id 14489 rev 2 43/64 tsc_fraction_z touch screen controller fraction_z address: 0x56 type: r reset: 0x00 description: this register allows to select the range and accuracy of the pressure measurement 76543 2 1 0 reserved fraction_z [7:3] reserved [2:0] fraction_z : 000: fractional part is 0, whole part is 8 001: fractional part is 1, whole part is 7 010: fractional part is 2, whole part is 6 011: fractional part is 3, whole part is 5 100: fractional part is 4, whole part is 4 101: fractional part is 5, whole part is 3 110: fractional part is 6, whole part is 2 111: fractional part is 7, whole part is 1
touch screen controller stmpe811 44/64 doc id 14489 rev 2 tsc_i_drive touch screen controller drive i address: 0x58 type: r/w reset: 0x00 description: this register sets the current limit value of the touch screen drivers tsc_shield touch screen controller shield address: 0x59 type: r reset: 0x00 description: writing each bit would ground the corresponding touch screen wire 76543 2 1 0 reserved drive [7:1] reserved [0] drive : maximum current on the touch scree n controller (tsc) driving channel 0: 20 ma typical, 35 ma max 1: 50 ma typical, 80 ma max 76543 2 1 0 reserved x+ x- y+ y- [7:4] reserved [3:0] shield[3:0] : write 1 to gnd x+, x-, y+, y- lines
stmpe811 touch screen controller programming sequence doc id 14489 rev 2 45/64 11 touch screen controller programming sequence the following are the steps to configure the touch screen controller (tsc): a) disable the clock gating for the touch screen controller and adc in the sys_cfg2 register. b) configure the touch screen operating mode and the window tracking index. c) a touch detection status may also be enabled through enabling the corresponding interrupt flag. with this interrupt, the user is informed through an interrupt when the touch is detected as well as lifted. d) configure the tsc_cfg register to specify the ?panel voltage settling time?, touch detection delays and the averaging method used. e) a windowing feature may also be enabled through tscwdwtrx, tscwdwtry, tscwdwblx and tscwdwbly registers. by default, the windowing covers the entire touch panel. f) configure the tsc_fifo_th register to specify the threshold value to cause an interrupt. the corresponding interrupt bit in the interrupt module must also be enabled. this interrupt bit should be masked off during data fetching from the fifo in order to prevent an unnecessary trigger of this interrupt. upon completion of the data fetching, this bit can be re-enabled g) by default, the fifo_reset bit in th e tsc_fifo_ctrl_sta register holds the fifo in reset mode. upon enabling the touch screen controller (through the en bit in tsc_ctrl), this fifo reset is automatically deasserted. the fifo status may be observed from the tsc_fifo_ctrl_sta register or alternatively through the interrupt. h) once the data is filled beyond the fifo threshold va lue, an interrupt is triggered (assuming the corresponding interrupt is being enabled). the user is required to continuously read out the data set until the current fifo size is below the threshold, then, the user may clear the interrupt flag. as long as the current fifo size exceeds the threshold value, an interrupt from the touch screen controller is sent to the interrupt module. therefore, even if the interrupt flag is cleared, the interrupt flag will automatica lly be asserted, as long as the fifo size exceeds the threshold value. i) the current fifo size can be obtained from the tsc_fifo_sz register. this information may assists the user in how many data sets are to be read out from the fifo, if the user intends to read all in one shot. the user may also read a data set by a data set. j) the tsc_data_x register holds the x-coordinates. this register can be used in all touch screen operating modes. k) the tsc_data_y register holds the y-coordinates. tsc_data_y register holds the y-coordinates. l) the tsc_data_z register holds the z value. tsc_data_z register holds the z- coordinates. m) the tscdata_xyz register holds the x, y and z values. these values are packed into 4 bytes. this register can only be used when the touch screen operating mode is 00 0 and 001. this register is to facilitate less byte read. n) for the tsc_fract_z register, the user may configure it based on the touch screen panel resistance. this allows the user to specify the resolution of the z
touch screen controller programming sequence stmpe811 46/64 doc id 14489 rev 2 value. with the z value obtained from the register, the user simply needs to multiply the z value with the touch screen panel resistance to obtain the touch resistance. o) the tsc_data register allows facilitatio n of another reading format with minimum i 2 c transaction overhead by using the non autoincrement mode (or equivalent mode in spi). the data format is the same as tsc_data_xyz, with the exception that all the data fetched are from the same address. p) enable the en bit of the tsc_ctrl register to start the touch detection and data acquisition. q) during the auto-hibernate mode, a touch detection can cause a wake-up to the device only when the tsc is enabled and the touch detect status interrupt mask is enabled. r) in order to prevent confusion, it is recommended that the user not mix the data fetching format (tsc_data_x, tsc_data_y, tsc_data_z, tsc_data_xyz and tsc_data) between one reading and the next. s) it is also recommended that the user should perform a fifo reset and tsc disabling when the adc or tsc setting are reconfigured.
stmpe811 temperature sensor doc id 14489 rev 2 47/64 12 temperature sensor the stmpe811 internal temperature sensor can be used as a reference for compensation of the touch screen parameters. temperature measurement is optimised for temperature from 0 c to 85 c. temp_ctrl temperature sensor setup address: 0x60 type: r/w reset: 0x00 description: temperature sensor setup table 17. touch screen parameters address register name bit function 0x60 temp_ctrl 8 temperature sensor setup 0x61 temp_data 16 temperature data access port 0x62 temp_th 16 threshold for te mperature controlled interrupt 765 4 3 2 1 0 reserved thres_range thres_en acq_mod acq enable [7:5] reserved [4] thres_range : '0' assert interrupt if te mperature is >= threshold '1' assert interrupt if otherwise [3] thres_en : temperature threshold enable [2] acq_mod : '0' to acquire temperature for once only '1' to acquire temperature every 10ms [1] acq [0] enable
temperature sensor stmpe811 48/64 doc id 14489 rev 2 temp_data temperature data address: 0x61 type: r reset: 0x00 description: temperature data access port temp_th temperature threshold address: 0x62 type: r/w reset: 0x00 description: threshold for temperature controlled interrupt 11109876543 2 1 0 temperature [11:0] temperature : temperature reading absolute temperature = ( v io * temperature [11:0] ) / 7.51 (12-bit adc) = ( v io * temperature [9:0] ) / 7.51 (10-bit adc) note that v io is used as a reference in temperature acquisition. variations in v io will directly affect the accuracy of temperature acquired. 11109876543 2 1 0 temp_th [11:0] temp_th : temperature threshold
stmpe811 gpio controller doc id 14489 rev 2 49/64 13 gpio controller a total of 8 gpios are available in the stmpe811 port expander device. most of the gpios share physical pins with some alternate functions. the gpio controller contains the registers that allow the host system to configure each of the pins into either a gpio, or one of the alternate functions. unused gpios should be configured as outputs to minimize power consumption. a group of registers are used to control the exact function of each of the 8 gpios. the registers and their respective addresses are listed in the following table. all gpio registers are named as gpio-x, where x represents the functional group. table 18. gpio control registers address register name size (bit) function 0x10 gpio_set_pin 8 set pin register 0x11 gpio_clr_pin 8 clear pin state 0x12 gpio_mp_sta 8 monitor pin state 0x13 gpio_dir 8 set pin direction 0x14 gpio_ed 8 edge detect status 0x15 gpio_re 8 rising edge detection enable 0x16 gpio_fe 8 falling edge detection enable 0x17 gpio_alt_funct 8 alternate function register 76543 2 1 0 gpio-7 gpio-6 gpio-5 gpio-4 gpio-3 gpio-2 gpio-1 gpio-0
gpio controller stmpe811 50/64 doc id 14489 rev 2 gpio_set_pin gpio set pin register address: 0x10 type: r/w reset: 0x00 description: gpio set pin register. writing 1 to this bit causes the corresponding gpio to go to 1 state. writing 0 has no effect. gpio_clr_pin clear pin state register address: 0x11 type: r/w reset: 0x00 description: gpio clear pin state register. writing ?1? to this bit causes the corresponding gpio to go to 0 state. writing ?0? has no effect. gpio_mp_sta gpio monito r pin state register address: 0x12 type: r/w reset: 0x00 description: gpio monitor pin state. reading this bit yields the current state of the bit. writing has no effect. gpio_dir gpio set pin direction address: 0x13 type: r/w reset: 0x00 description: gpio set pin direction register. writing ?0? sets the corr esponding gpio to input state, and ?1? sets it to output state. all bits are ?0? on reset.
stmpe811 gpio controller doc id 14489 rev 2 51/64 gpio_ed_sta gpio edge detect status address: 0x14 type: r/w reset: 0x00 description: gpio edge detect status register. an edge transition has been detected. gpio_re rising edge register address: 0x15 type: r/w reset: 0x00 description: gpio rising edge detection enable register. setting this bit to ?1? would enable the detection of the rising edge transition. the detection would be reflected in the gpio edge detect status register. gpio_fe falling edge detect ion enable register address: 0x16 type: r/w reset: 0x00 description: setting this bit to ?1? would enable th e detection of the falling edge transition. the detection would be reflected in the gpio edge detect status register. gpio_alt_funct alternate function register address: 0x17 type: r/w reset: 0x0f description: alternate function register. "?0? sets the corresponding pin to function as touch screen/adc, and ?1? sets it into gpio mode. 13.0.1 power supply the stmpe811 gpio operates from a separate supply pin (v io ). this dedicated supply pin provides a level-shifting feature to the stmpe811. the gpio remains valid until v io is removed. the host system may choose to turn off v cc supply while keeping v io supplied. however it is not allowed to turn off supply to v io , while keeping the vcc supplied. the touch screen is always powered by v io . for better resolution and noise immunity, v io above 2.8 v is advised.
gpio controller stmpe811 52/64 doc id 14489 rev 2 13.0.2 power-up reset (por) the stmpe811 is equipped with an internal por circuit that holds the device in reset state, until the v io supply input is valid. the in ternal por is tied to the v io supply pin. on power-up reset, all gpios are set as input.
stmpe811 maximum rating doc id 14489 rev 2 53/64 14 maximum rating stressing the device above the ratings listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect the device?s reliability. table 19. absolute maximum ratings symbol parameter value unit v cc supply voltage 4.5 v v io gpio supply voltage 4.5 v esd esd protection on each gpio pin (air discharge) 4 kv t operating temperature -40 - 85 c t stg storage temperature -65 - 155 c t j thermal resistance junction-ambient 96 c/w
maximum rating stmpe811 54/64 doc id 14489 rev 2 14.1 recommended op erating conditions table 20. power consumption symbol parameter test condition value unit min typ max vcc core supply voltage vio >= vcc 1.65 ? 3.6 v v io i/o supply voltage 1.65 ? 3.6 v i cc-active core supply current touch screen controller at 100 hz sampling v cc =1.8 ? 3.3 v ? 0.5 1.0 a i io-active i/o supply current touch screen controller at 100 hz sampling v io =1.8v ? 0.8 1.2 ma i io-active i/o supply current touch screen controller at 100 hz sampling v io =3.3v ? 2.0 2.8 ma i cc- hibernate core supply current hibernate state, no i2c/spi activity v cc =1.8v ? 0.5 1 a i io-hibernate i/o supply current hibernate state, no i2c/spi activity v io =1.8 ? 3.3 v ? 0.5 1 a hibernate state, no i2c/spi activity v io =3.3v ? 1.0 3.0 a
stmpe811 electrical specifications doc id 14489 rev 2 55/64 15 electrical specifications table 21. dc electrical characteristics (-40 c to 85 c) all gpios comply to jedec standard jesd-8-7) table 22. ac electrical characteristics (-40 c to 85 c) symbol parameter test condition value unit min typ max v il input voltage low state v io =1.8 ? 3.3 v -0.3 v ? 0.20 v io v v ih input voltage high state v io =1.8 ? 3.3 v 0.80 v io ? v io +0.3v v v ol output voltage low state v io = 1.8 v, i ol = 4 ma v io = 3.3 v, i ol = 8 ma -0.3 v ? 0.15 v io v v oh output voltage high state 0.85 v io ?? v v ol (i 2 c/spi) output voltage low state v cc = 1.8 v, i ol = 4 ma v cc = 3.3 v, i ol = 8 ma -0.3 v ? 0.15 v cc v v oh (i 2 c/spi) output voltage high state 0.85 v cc ? v cc +0.3v v symbol parameter test condition value unit min typ max clki2c max i 2 c maximum sclk v io =1.8-3.3v 400 ?? khz clkspi max spi maximum clock v io =1.8v 800 ?? khz v io = 3.3 v 1000 ?? khz
electrical specifications stmpe811 56/64 doc id 14489 rev 2 table 23. adc spec ification (-40 c to 85 c) table 24. switch drivers specification table 25. voltage reference specification parameter test condition value unit min typ max full-scale input span 0 ? v ref v absolute input range ?? v cc +0.2 v input capacitance ? 25 ? pf leakage current ? 0.1 ? a resolution ? 12 ? bits no missing codes 11 ? bits integral linearity error ? 4 ? bits offset error ? 5 ? lsb gain error ? 14 18 lsb noise including internal v ref ? 70 ? vrms power supply rejection ratio ? 50 ? db throughput rate ? 180 ? ksps parameter test condition value unit min typ max on resistance x+, y+ ? 5.5 ? on resistance x-, y- ? 7.3 ? drive current duration 100 ms ?? 50 ma parameter test condition value unit min typ max internal reference voltage 2.45 2.50 2.55 v internal reference drift ? 25 ? ppm/c output impedance internal reference on ? 300 ? internal reference off ? 1 ? g
stmpe811 package mechanical data doc id 14489 rev 2 57/64 16 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data stmpe811 58/64 doc id 14489 rev 2 figure 12. package outline for qfn16 (3x3x 1 mm) - 0.50 pitch 1. drawing not to scale. 71 8 5 33 0_f
stmpe811 package mechanical data doc id 14489 rev 2 59/64 table 26. package mechanical data for qfn16 (3 x 3 x 1 mm) - 0.50 pitch symbol millimeters min typ max a 0.80 0.90 1.00 a1 ? 0.02 0.05 a3 ? 0.20 ? b 0.18 0.25 0.30 d 2.85 3.00 3.15 d1 ? 1.50 ? d2 see exposed pad variation e 2.85 3.00 3.15 e1 ? 1.50 ? e2 see exposed pad variation e 0.45 0.50 0.55 l 0.30 0.40 0.50 ddd ?? 0.05 table 27. exposed pad variation symbol millimeters min typ max d2 1.70 1.80 1.90 e2 1.70 1.80 1.90
package mechanical data stmpe811 60/64 doc id 14489 rev 2 figure 13. recommended footprint 1. drawing not to scale. table 28. footprint dimensions symbol millimeters min typ max a ? 3.8 ? b ? 3.8 ? c ? 0.5 ? d ? 0.3 ? e ? 0.8 ? f ? 1.5 ? g ? 0.35 ?
stmpe811 package mechanical data doc id 14489 rev 2 61/64 figure 14. carrier tape for qfn16 (3 x 3 x 1 mm) - 0.50 pitch 1. drawing not to scale. 7 8 7597 8
package mechanical data stmpe811 62/64 doc id 14489 rev 2 figure 15. reel information for qfn16 (3 x 3 x 1 mm) - 0.50 pitch 1. drawing not to scale. 7 8 7597 8 _14
stmpe811 revision history doc id 14489 rev 2 63/64 17 revision history table 29. document revision history date revision changes 09-jun-2008 1 initial release. 22-apr-2009 2 document status prom oted from preliminary data to datasheet. modified: title and package silhouette in the cover page. section 6: stmpe811 registers , section 7: system and identification registers , section 10: touch screen controller and section 13: gpio controller : content reworked to improve readability, no technical changes. updated: figure 6 , ta bl e 3 , section 14: maximum rating and section 16: package mechanical data .
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